1. Field of the Invention
The present invention relates generally to computer devices. More specifically, the present invention relates to dynamically setting a system clock rate of a computer system based on outstanding commands needing to be executed.
2. Description of the Related Art
Processors in a computer system operate at a certain clock rate. The clock rate is the rate (typically measured in cycles per second or hertz) for the frequency of the clock. Typically a processor can execute a certain number of commands per cycle, so the clock rate roughly equates to the number of commands the processor is capable of handling per second (although since each processor can be capable of executing a different number of commands per cycle, using the clock rate as a comparison between processor architectures generally is not helpful).
Some processors offer the ability to dynamically alter their clock rate. For example, the Intel SpeedStep™ processor can slow down or speed up its clock rate at runtime. This allows the processor to meet the instantaneous performance needs of the operation being performed, while minimizing power draw and heat dissipation.
Prior art techniques, however, base the dynamic processor speed on the current load of the processor (i.e., how busy the processor is). When the processor is not busy, the clock rate is adjusted downwards to save power and reduce heat dissipation. When the processor gets busy again, the clock rate is adjusted back upwards to meet the demand.
This technology can work well in the case of processors themselves, but certain devices contain multiple modules that share a system clock. For example, a Universal Serial Bus (USB)-to-Serial ATA (SATA) bridge device may contain a processor, memory, a redundant array of independent disks (RAID) engine, an encryption core, etc., all of which may be linked to the same system clock. Altering the processor's clock rate alone based on the load of the processor is simply not feasible in such an architecture, since these components may require matching clock rates in order to operate at peak efficiency (i.e., avoid excessive delays in processing commands).
This problem is amplified even further in USB3.0-to-SATA bridges. For high performance, it is necessary to clock the system of such a bridge to a high clock rate to meet the high USB3.0 burst rate of 500 MBps. This high system clock rate utilizes a significant amount of power.